This invention relates to the fabrication of integrated circuits semiconductor devices and, more particularly, to forming an insulating layer on and between metal conductive lines which provide an interconnection between the active and/or passive elements of the integrated circuit and other levels of interconnection.
In very large scale integrated (VLSI) circuit devices, several wiring layers are required to connect together the active and/or passive elements in a VLSI semiconductor chip. The interconnection structure consists of thin conductive lines separated by insulation in one layer or level and connected through vias or studs from contacts of the elements of the semiconductor chip or to a similar layer in another level of interconnections. This interconnection structure is similar to a transmission line in that there is a propagation delay of the signals being transmitted in these wiring layers. The delay is referred to as RC delay because it is a result of the resistance (R) of the material of the wire and the capacitance (C) between adjacent wires. With the trend of higher and higher levels of integration in semiconductor devices to ultra large scale integrated (ULSI) circuits, the space or gap between the wires or conductive lines to be filled with insulation is becoming extremely narrow between some of the conductive lines, such as about 0.5 microns and smaller. Such a narrow space or gap between conductive lines increases the capacitance and places greater demands on the insulating properties of the insulation between the conductive lines. Capacitance (C) is the product of dielectric constant (DC) of the insulating material times the area (A) of the opposing faces of the conductive lines divided by the distance (D) between the conductive lines. With a decrease in distance (D) or the gap between conductive lines, the capacitance (C) increases. Since signal delay of signal transmitted on the conductive line is controlled by the RC constant, an increase in capacitance (C) degrades the performance of the integrated circuit.
At the present state of the art, the insulating material used to fill these gaps is a silicon compound, such as silicon dioxide, which has a dielectric constant (DC) of between 3.5 and 4.0. A vacuum has a perfect dielectric constant (DC) and is the basis for the measurement of the dielectric constant of materials. For example, air and other insulating gases have a dielectric constant (DC) of about 1 or slightly less than 1. The use of insulating material with dielectric constants (DC) lower than 3.5 in the narrow gap will lower the capacitance (C) and offset the increase caused by the smaller distance (D) between adjacent conductive lines. Attempts have been made to use organic insulating materials, such as polyimides which have a DC of between 3.2-3.4, but are hydroscopic and any absorbed moisture can potentially cause corrosion of metal lines.
In addition to the demands placed on the insulating property of the insulation between the conductive lines, these narrow gaps of about 0.5 microns and smaller make it much more difficult to deposit the insulating material into the gaps so that the gaps may not be completely and properly filled. In addition, when the height of the conductive line is increased, it makes it more difficult to fill, especially when the aspect ratio is 2 to 1 or greater with a gap distance of 0.5 microns or smaller. Aspect ratio is the height (h) of the conductive line divided by the distance (d) or gap between the conductive lines. It is pointed out in U.S. Pat. No. 5,124,014 to Pang-Dow Foo et al. that when the gap or distance (d) is less than the height (h) of the conductive line, it is difficult to fill uniformly. This patent states that the top tends to accumulate deposited material, growing shoulders that may eventually close off before the bottom is filled, leading to the formation of voids in the deposited material. U.S. Pat. No. 5,275,977 to Otsubo et al. confirms this problem and sets the same objective for their process as Pang-Dow Foo et al.; namely, the formation of the insulating film free of voids. This patent discloses the combination of chemical vapor deposition (CVD) and etching a silicon dioxide film (SiO.sub.2) using tetraorthosilicate (TEOS) [Si(OC.sub.2 H.sub.5).sub.4 ] as the source silicon gas and oxygen (O.sub.2) for deposition of SiO.sub.2 and carbon tetrafluoride (CF.sub.4) as the etching gas. With TEOS as the source gas, the deposited SiO.sub.2 films are conformal in that the deposition follows the contour of the surface on which it is being deposited. This patent also suggests the use of other source gases, one of which is silane (SiH.sub.4). However, other than this suggestion, no description is given for forming an insulating layer between and on the conductive lines with SiH.sub.4 as the source. The Pang-Dow Foo et al. patent describes the use of an electron cyclotron resonance (ECR) plasma reactor, which can be operated to both deposit and sputter etch either simultaneously or sequentially, to deposit high quality silicon dioxide layers which are void-free. The deposition of SiO.sub.2 occurs in a vertical direction while the sputtering is angle dependent, with its highest yield being at 45.degree.. Instead of SiH.sub.4, either TEOS or tetramethycyclosiloxane (TMCTS) is used as the silicon containing source gases. Both of these source gases produce conformal films. This patent states that as the aspect ratio approaches and exceeds unity, it becomes more difficult to deposit void-free oxide. To prevent voids in the insulating layer in filling these narrow gaps, the bias potential is increased to induce a greater amount of sputter etching. Alternatively, a separate etching step may be performed.
One advantage of using ECR plasma deposition is that the substrate does not have to heated to more than 150 degrees C. Above about 400 degrees C., hillocks tend to form in the aluminum conductive lines and, if the growth is lateral, it could bridge the narrow gap between lines and create a short.
The description in the specification both of these patents describes methods for forming void-free insulating layers between the conductive lines and teaches that, from a detrimental standpoint, voids will form in the gaps between the conductive lines under certain conditions without describing the size or position of these voids.